This invention relates to programmable logic devices, and more particularly, this invention relates to the testing, programming and verification of programmable logic devices which employ non-volatile electrically erasable programmable transistors.
Programmable logic devices provide flexible logic function architecture, which is user-programmable through on-chip fuses or switches, to perform specific functions for a given application. PLDs can be tailored to a desired logic configuration after being purchased by the customer.
Programmable logic devices can be programmed in different ways. One way is to use a special programmer such as the PDS-3 programmer (a machine manufactured by ICT, Inc.). When this method is used, signals are sent in parallel to the memory cells. In this situation no dedicated pins are needed for program and test. Another way is `in-system` programming by which PLDs may be programmed after they have been installed as part of a larger assembly, e.g. after they have been assembled with other components on a printed circuit board. They may be reprogrammed without being removed from the board. They are programmed or erased through a small number of pins on the PLD device. An example of this method is the use of a JTAG interface. This interface is specified as the IEEE Standard Test Access Port and Boundary-Scan Architecture, in IEEE Standard 1149.1-1990. JTAG programming uses four dedicated pins on the PLD. Signals to these pins are typically TMS (test mode select), TCK (test clock), TDI (test data in), and TDO (test data out). This method avoids the alternative of having to use complex system sources for programming or erasing.
Generally, to guarantee quality and performance of a device, a number of test procedures should be performed before a programmable device is programmed for a specific application function. For memory-based programmable logic devices, tests usually include: memory cell current reading test, checker board test, address decode test, softwrite test and logic function test. In all memory-based devices, including EPROM, EEPROM and flash memory, configuration information is stored in the memory cell. This information is read out as current, which is amplified by a sense amplifier and converted to a voltage signal. If the current reading of a cell is too large, power consumption of the device will be too high. If the current is too low, the reliability of the device will be a problem and production quality control will be difficult. Because of the realities of fabrication, it is impossible that every chip of a device on a die will have the same memory cell current reading as specified by the design. The memory cell current test provides accurate data which reflect the actual status of memory cell operation.
In memory-based devices, memory cells are usually placed as an array of columns and rows, resulting in gates of adjacent cells being very close to each other. This structure makes it possible for adjacent cells to be short circuited. Checkerboard and Inverse Checkerboard tests can detect a short circuit by programming the cell array into certain check patterns and then verifying them.
A logic function test is usually done by programming a device in certain complex logic function circuits, such as an inverter or a counter, or a combination of several simple logic circuits. This facilitates functional testing of the device. The preloading of the registers allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, illegal states can be verified by loading illegal states and observing proper recovery.
Softwrite is a test condition in which low programming voltage and low Vcc are used. Some devices need to be tested under this condition in order to guarantee that a PLD device will work normally in a worst case scenario. This is done using complex test equipment and has disadvantages, such as increasing the complexity of the test procedure and slowing the test process. Special configuration memories and control circuits are designed to control the voltage and complement this test.
Address decoder test is important and is a regular test process for PLDs at the sorting and final testing phases. As PLD density increases, and as architecture becomes more complex, the number of address decoders increases greatly, and time for decoder test increases considerably. It is therefore expeditious to add a special Decode instruction and design a circuit to achieve on-chip decoder testing.
Different tests use different pins multiplexed between the test state and normal operation. Different tests use different internal circuit structures. Some tests require different external connections. It may be necessary to place the device in normal operation, programming and testing mode by applying several control signals separately to avoid signal contention on the device. It may also be necessary to apply a particular programming or erasing potential to the device, which potential may be different from potentials normally applied to the device. Consequently, a device with different test items requires more system resources for programming, verifying and testing. However, test could be considered as a series of combination operations of programming and erasing. It is desirable to implement the test functions in a programming structure by employing the in-system programmability through a port such as the JTAG port so that additional pins do not have to be used for applying other programming or erasing mode control signals and/or for applying special programming or erasing potentials, in order to avoid having to use more extensive system resources. With the testing and programming sharing the same programming structure, the states of the device can be switched easily. The application of the particular potential required by reading, programming and erasing can be controlled by the controller of the structure. The interface with external is very simple, which greatly reduces the external connections.
In view of the foregoing, it is an object of this invention to provide an improved testing compatible programming structure for the programming of programmable logic devices through a test port, such as a JTAG test access port.
It is another object of this invention to improve and simplify the testing of programmable logic devices by integrating the test function into the programming structure.